Many types of processor, memory, bus, and other resource configurations have been utilized in the prior art to provide parallel and pipeline processing. These configurations include systems for multiple processors to utilize shared memory or systems for processors to share a parallel workload.
Various configurations and techniques used for parallel and pipeline processing are described below.
U.S. Pat. No. 4,930,102 is directed to a computer architecture utilizing parallel processors that includes an interface system between the various physical components and a queueing structure for holding waiting activities. More specifically, this computer architecture includes a cross-bar circuit and a accordian-store queue structure.
U.S. Pat. No. 4,920,487 is directed to a parallel processing computer system with multiple processing units and shared memory which balances the aggregate computational load by utilizing a network having identical computations to be executed at each connection therein.
U.S. Pat. No. 4,875,161 is directed to a vector file organization to support multiple program execution pipelines. Each of the pipelines can simultaneously access various blocks of a vector file through segmenting the file storage and by addressing the various elements of the segments.
U.S. Pat. No. 4,850,027 is directed to an image processing system with limited processing element connections that provides many image processing network choices without massive memory and bus capacity.
U.S. Pat. No. 4,839,798 is directed to a computer network system with a plurality of online connected computer systems. Each computer system can request transfer of a job to another computer system.
U.S. Pat. No. 4,814,978 is directed to a computer design utilizing large numbers of VLSI circuit chips. This design is a static dataflow architecture in which a plurality of processing elements communicate externally by means of I/O circuitry and internally by means of packets sent through a routing network that implements a transmission path from any processing element to any other processing element.
U.S. Pat. No. 4,766,566 is directed to a RISC type VLSI processor using dual parallel execution units. The load between the dual units may be balanced by adding an adder, a multiplier, or an ALU to the units.
U.S. Pat. No. 4,736,291 is directed to a general purpose array processor which includes a plurality of independent processing units for processing seismic data stored in a bulk memory. A digital host computer provides the overall control of the system through a host interface unit.
U.S. Pat. No. 4,633,387 is directed to a multiunit data processing system, such as a multicontrol unit peripheral data storage system, in which a busier unit may transfer work to a less busy unit based on a request for work from the less busy unit.
U.S. Pat. No. 4,543,626 is directed to a control arrangement for coordinating operations of multiple processors in a multiprocessor system in response to a command. Each received command is associated with a predetermined route including route vectors. A control block is generated for the route. Each route vector identifies an operation to be executed and the station to execute the operation. Each station has a work queue containing control blocks which the station retrieves and processes sequentially.
U.S. Pat. No. 4,504,909 is directed to an array processor for real time processing of acquired data from a CT scanner. In this system, processing of subportions of a given array is interleaved with inputting of acquired data sets for the next array.
U.S. Pat. No. 4,495,562 is directed to a controlling method for a parallel processing system wherein the used time periods of a processor are periodically measured for determining workloads.
U.S. Pat. No. 4,493,020 is directed to a microprogrammed data processing system in which each high level instruction is performed by one or more tasks and each task is then performed by executing one or more task microinstructions in a microprogrammed manner. Three separate processors operate 120 degrees out of phase with each other while sharing the same physical hardware such as memory. Resources to the processors are allocated on demand based on the status of allocatable registers.
U.S. Pat. No. 4,493,019 is directed to a microprogrammed data processing system having a three stage high point architecture implemented for executing microinstructions using three separate processors operating 120 degrees at a phase with one another.
U.S. Pat. No. 4,384,324 is directed to a microprogrammed data processing system having a three stage high point architecture implemented for executing microinstructions using three separate processors operating 120 degrees at a phase with one another.
U.S. Pat. No. 4,229,790 is directed to a system for concurrent processing of tasks and instructions. The processor is a multiple instruction multiple data screen digital computer that utilizes pipelining for control and function units but avoids precedence constraint penalties.
U.S. Pat. No. 3,905,023 is directed to a multiprogrammed multiprocessing information processing system having independently operating computing, I/O and memory modules through an exchange.